USB 3.0 Host Controller

Sibridge's USB 3.0 Host Controller is a high performance, low gate count, xHCI 1.0 compliant semiconductor IP designed for SuperSpeed USB host implementations in ASIC and FPGA and engineered for deep submicron process nodes and smaller geometries.

The controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0. The controller includes multiple user interfaces options including AMBA AHB/AXI.

The block diagram below above provides a high level overview of the architecture of the host IP. The Host controller can be connected to either an AHB/AXI bridge or a custom bridge. The USB 3.0 Host IP core is compliant with USB 3.0 specification revision 1.0.

The core is compliant with the Intel® PIPE interface for USB 3.0, this allows the core to be integrated with PIPE-complaint PHY layers and also support SSIC interface.

  • 5/10 Gbps, 480 Mbps, 12 Mbps, 1.5 Mbps
  • Superspeed USB 3.0 Specifications, Rev1.0
  • xHC specification, Rev1.00
System Bus Interface
  • AHB 2.0, AHB-Lite interface
  • Multi-channel AXI 2.0 interface
  • Supports custom 32-bit data path
USB Bus Interface
  • 16/32 bit USB 3.0 PIPE interface
  • SSIC support
  • USB Rev2.0 UTMI/ULPI interface
  • Seamless integration to various USB 3.0 PHY device/IC
  • Optional Asynchronous clocking between Core and user interface logic(CDC)
  • System bus clock speed up to 333 Mhz
  • Supports 32-bit Backend interface Full Power Management support (U1, U2, U3), LFPS
USB 3.0 Special Features
  • Includes Physical, Link, and Protocol layers
  • Supports Bulk with streaming, Control, INT, Isochronous Endpoints
  • Configurable buffer sizes
  • Configurable USB Specification timeout counters Interface
  • Supports 15 IN and OUT Endpoints and 1 control Endpoint
  • High speed DMA transfer using xHC core
  • USB3 PCIe bridge solution with reference design (optional)
  • Host controller verification environment in SystemVerilog with USB 3.0 VIP (optional)


  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation