USB 3.0 Device Controller

Sibridge's USB 3.0 Device Controller is a high performance, low gate count, XDC compliant semiconductor IP designed for SuperSpeed in SuperSpeed USB device implementations ASIC and FPGA and engineered for deep submicron process nodes and smaller geometries.

The controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0. User interfaces options include AMBA 2 AHB and a proprietary high-performance DMA.

The diagram below provides a high level overview of the architecture of the device IP. The USB 3.0 device IP seamlessly integrates with wide range of USB 3.0 PHY IP.

The core is compliant with the Intel® PIPE interface for USB 3.0, this allows the core to be integrated with PIPE-complaint PHY layers and also support SSIC interface.

  • Super-speed USB 3.0 Specification, Rev1.0
  • Full support for legacy USB 2.0
System Bus Interface
  • Supports 64-bit data-path custom interface
  • AMBA2 AHB, AHB-Lite Interface
USB Bus Interface
  • Support 16/32 bit PIPE interface
  • SSIC support
  • USB Rev2.0 UTMI/ULPI interface
  • Seamless integration to various USB 3.0 PHY device/IC
  • Optional Asynchronous clocking between Core and user interface logic(CDC)
  • Core clock speed 62.5 MHz
  • Supports 32-bit Backend interface Full Power Management support (U1, U2, U3), LFPS
USB 3.0 Special Features
  • Includes Physical, Link, and Protocol layers
  • Supports Bulk with streaming, Control, INT, Isochronous Endpoints
  • Configurable buffer sizes
  • Configurable USB Specification timeout counters Interface
  • Supports user configurable up to 16 IN and OUT Endpoints
  • USB3 PCIe bridge solution with reference design (optional)


  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation