PCI Express Design IP

PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. Sibridge Technologies offers a highly configurable and Silicon Proven PCI Express core.

  • x1, x4, x8 Lanes 
  • Root Port, Endpoint, Shared Silicon (RP / EP) configurations 
  • PCI Express 1.1  compliant 
  • Supports Intel PIPE 8/16-bit interface 
  • Virtual Channels: 1-8 (client determines credits for each) 


  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation