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Serial ATA Device Controller
Chip Verification Services


SATA Device Controller Design IP Block Diagram


  • Compliant with the Serial ATA specification version 2.6
  • Supports 1.5 Gb/s (150 MB/s) or 3 Gb/s (300 MB/s) speeds
  • Software-compatible with parallel ATA
  • Supports Native Command Queuing (NCQ)
  • Support for Spread Spectrum Clocking (SSC)
  • Auto-read and auto-write
  • Integrated DMA controller
  • Supports 20-bit SATA standard PHY interface
  • Asynchronous Notification
  • Supports either CoreFrame or AMBAAHB 2.0 bus interface

 

 

Deliverables

  • Verilog Source code
  • Functional test bench
  • Synthesis Constraint files
  • Product specifications and user/programmer's guide

Best-in-class Support for IP

  • Team with protocol and design expertise
  • IP integration support and services
  • Portfolio of Verification IP in SystemVerilog
  • Driver development and firmware validation
  • FPGA emulation and prototyping

Other IPs

Ethernet 10/100/1000 Mbps

USB OTG
Serial ATA Host Controller
Parallel ATA device controller
PCMCIA
Gigabit Ethernet VIP
I2C Verification IP

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