Chip Design & Chip Verification Company
 


Serial ATA Host Controller
Chip Verification Services


SATA Design IP Block Diagram


  • Compliant with serial ATA version 2.6
  • 1.5 Gbps or 3 Gbps speed
  • Compatible with Intel register Set
  • 10-20-40 bit SATA standard PHY interface
  • Native Command Queuing and spread spectrum clocking
  • DMA interface for data transfer
  • CoreFrame or AMBA AHB 2.0 interface

 

 

Deliverables

  • Verilog Source code
  • Functional test bench
  • Synthesis Constraint files
  • Product specifications and user/programmer's guide

Best-in-class Support for IP

  • Team with protocol and design expertise
  • IP integration support and services
  • Portfolio of Verification IP in SystemVerilog
  • Driver development and firmware validation
  • FPGA emulation and prototyping

Other IPs

Ethernet 10/100/1000 Mbps

USB OTG
Serial ATA Host Controller
Parallel ATA device controller
PCMCIA
Gigabit Ethernet VIP
I2C Verification IP

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