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I2C Bus Interface
Master slave operations with multi master system support
10 bit addressing with I2C bus
Supports fast mode with speed 400Kbits/sec
Supports own address and general call address detection with interrupt on address detection
Synchronous processor interface with arbitration and clock synchronization
Fully synthesizable IP
Deliverables
Verilog Source code
Functional test bench
Synthesis Constraint files
Product specifications and user/programmer's guide
Best-in-class Support for IP
Team with protocol and design expertise
IP integration support and services
Portfolio of Verification IP in SystemVerilog
Driver development and firmware validation
FPGA emulation and prototyping
Other IPs
Ethernet 10/100/1000 Mbps
USB OTG
Serial ATA Host Controller
Parallel ATA device controller
PCMCIA
Gigabit Ethernet VIP
I2C Verification IP
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