Chip Design & Chip Verification Company
 


Ethernet 10/100/1000 Mbps MAC
Chip Verification Services

10 Gigabit Ethernet block diagram

  • Meets IEEE 802.3, 802.3u/x/z/ac specifications.
  • Supports 10/100 Mbps with backpressure when operates in half duplex. Supports
  • 802.3x full duplex flow control.
  • Built in MII and GMII interface. Built in MII management.
  • 32 bit CPU interface with 8 bit MAC engine optimized for size and minimum latency.
  • Optional interface modules for RMII, SMII, RGMII, SGMII and TBI SERDES.
  • Fully synthesizable and scan insertion friendly design.
  • 10-Gigabit Ethernet MAC
    • XGMII Externder PCS layer (XAUI) for 10-Gigabit Ethernet
    • 64b/66b PCS sublayer (XSBI) for 10-Gigabit Ethernet BASE R applications
    • Statistics Module for Ethernet MAC
 



Deliverables

  • Verilog Source code
  • Functional test bench
  • Synthesis Constraint files
  • Product specifications and user/programmer's guide

Best-in-class Support for IP

  • Team with protocol and design expertise
  • IP integration support and services
  • Portfolio of Verification IP in SystemVerilog
  • Driver development and firmware validation
  • FPGA emulation and prototyping

Other IPs

Ethernet 10/100/1000 Mbps

USB OTG
Serial ATA Host Controller
Parallel ATA device controller
PCMCIA
Gigabit Ethernet VIP
I2C Verification IP

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