I2C Bus Interface

The SI-MI2CV provides an interface between a microprocessor and an I2C bus. It can be programmed to operate as either a master or a slave device and performs arbitration in master mode to allow it to operate in multi-master systems.


  • Master or slave operation
  • Multi-master systems supported
  • Allows 10-bit addressing with I2C bus
  • Performs arbitration and clock synchronization
  • Own address and General Call address detection


  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation