| |
|
| |
Ethernet standard features
- Fully compliant to IEEE std 802.3-2005
- Configurable for MAC and PHY Mode
- Supports Ports capable of Full Duplex or Half duplex mode
- Supports the management interface for all supported interfaces
- Supports flow control through pause frames
- Support frame types, including:
- MAC frames with length and EtherType interpretations of the length/type field
- VLAN-tagged frames
- MAC Control pause frames
- Jumbo frames
Extended capabilities
- Fully compliant with Mentor AVM3.0 (Easily extendable to OVM)
- Supports directed, constrained random and fully random testing mode
- Full support for generation of all kinds of data frame errors and protocol errors
- Full configurability for all the fields of Ethernet packet including length and data for every field
- Fully configurable to generate all kind of data payload including IPV4/6
- Monitors and checkers for protocol violations
- Coverage report generation
|
|
|
| |
|
| |
The GBE VIP is delivered in a full package containing:
- GBE VIP System Verilog encrypted source code
- User guide and release notes
- Test plan and Coverage plan
- Example of VIP usage
- Sample environment demonstrating various features
|
|
|
|
Overview
The Sibridge Gigabit Ethernet (GBE) Verification IP is a reusable, configurable, pre-verified, plug-and-play verification component developed in System Verilog. It offers a easy to use and complete verification solution for SoCs incorporating Ethernet MAC and PHY at module, chip and system level. The GBE VIP integrates automatic stimulus generation, assertion checking, and functional coverage analysis all within a single, extensible component.
GBE VIP provides a simple yet powerful user interface which drastically reduces the time and effort needed to create a verification environment and verify thoroughly to ensure first time right silicon. Using random stimulus generation and coverage driven methodology provided in GBE VIP, user can verify the design with few test cases in very short time instead of running thousands of directed test cases.
Architecture
 |
The GBE VIP is developed using System Verilog, the unified design and verification language. It is developed using a layered approach as shown in the figure below to bring out all advantages of System Verilog like full configurability, full and constrained random data generation, coverage driven verification approach, assertion based verification, etc. |
Applications
The GBE VIP can be used to verify any IEEE802.3 compliant MAC or PHY device. The VIP can be used for the functional verification of IP cores and SoC designs incorporating Ethernet MAC and PHY layer functionality. The VIP can also be used in Monitor mode where it will only monitor the interface and not drive any signal. This mode is particularly useful in system level testing.
Figure 1 here shows the typical verification enviornment for Ethenet MAC device. User will only need to develop Custom Interface logic to verify the design throughly using the Sibridge GBE VIP.
Figure 2 shows the typical verification environment for a Ethernet PHY device. With two instances of VIP, the user can verify the design thoroughly in a very short time.
|
