Ethernet Verification IP
Overview

The Sibridge Ethernet (ETH) Verification IP is a reusable, configurable, pre-verified, plug-and-play verification component developed in System Verilog. It offers easy to use and complete verification solution for SoCs incorporating Ethernet MAC and PHY at module, chip and system level. 



Features:
  • Supports Super speed (SS), High speed (HS), Full speed (FS) & Low speed (LS)
  • Support Host, Device and HUB/Interconnect port verification
  • Compliant to UTMI 8/16 & ULPI USB 2.0 specification
  • Complaint to PIPE 8/16/32 USB 3.0 specification


 


  • SystemVerilog Source Code
  • User Guide and Release Notes
  • Sanity Testcases
  • Test Plan + Coverage Plan [Upon Request]
  • Examples on topological usage
  • Sample Verification Environmenttion