Ethernet 10G Design IP
Ideal for Programmable Logic (FPGA) Implementations

The Sibridge Technologies 10-Gigabit Ethernet IP Layer 2 core provides a complete IEEE 802.3ae Ethernet Layer 2 solution. The completely integrated solution comprises a Logical Link Control, MAC Control, MAC, and reconciliation sublayer for a 10-Gbps interface between the Network Layer (Layer 3) and Physical Layer (Layer1) of the Ethernet OSI model.

  • Compliance with IEEE 802.3ae  
  • Support for IEEE 802.3x Full Duplex Flow control  
  • Support for 802.3ae XGMII  
  • Programmable Drop/Receive frame filter 
  • 33 statistics counters supporting RMON and EtherStats applications

  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation