DDR 2/3 Memory Controller Design IP

DDR 2/3 is the next generation of SDRAM memory technology. It is standardized by JEDEC through the JESD79-3C specification. DDR 2/3 DRAM memory controller supports multiple memory-clients with intelligent arbitration for maximum performance. The design supports high frequency, high performance AXI (Advanced extensible Interface) slave interface on one side and standard DFI interface on the DRAM side.

  • DDR  3 JEDEC standard, backward compatible with DDR 2
  • Support for OCP, AXI and AHB clients 
  • DRAM power down and self refresh during idle 
  • Fully programmable DRAM parameters 
  • Support for ECC if configured 


  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation