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Module to Chip Level verification
- Define verification strategy to ensure first time right
silicon
- Define the verification environment for all levels of
verification for maximum coverage
- Develop comprehensive test plans for module level and
chip level to achieve zero bugs.
- Develop module and chip level coverage plan for maximum
functions coverage with random testing.
- Develop highly efficient module and chip level verification
environment with maximum reusability.
- Integration of industry standard VIP for maximum productivity
gain.
- Development of module and chip level assertions.
- Develop efficient regression environment to reduce simulation time.
- Extensive experience in verification of SoCs with various
interfaces like USB, PCI Express, Ethernet, PCI, etc and
uPs like ARM, MIPS.
- Excellent experience in verification using SystemVerilog,
Vera, e, SystemC/C++, Verilog, VHDL and mixed languages.
Coverage driven verification
- Develop verification strategy based on industry standard
methodologies like VMM, RVM, AVM, eRM, UVM.
- Develop coverage plan for maximum functions coverage
with random testing.
- Develop environment for coverage driven verification
using SystemVerilog, Vera or e.
- Coverage development on legacy verification environment.
- Coverage plans for standard interfaces like USB, AHB,
PCI Express.
Assertion based verification
- White box assertion development for design IPs.
- Experience in development of Assertion IPs for standard
interfaces i.e. AHB, PCI, PCI Express, USB.
- Develop assertions using SVA, PSL and OVA.
Methodologies
- Develop verification strategy based on coverage driven
or directed test approach.
- Develop coverage verification strategy based on industry
standard methodologies like VMM, RVM, AVM, eRM, UVM.
- Develop unified verification solution using different
methodologies such as Verilog/VHDL, Coverage drive, assertion
based.
- Implement assertion based verification methodology.
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