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Audio-Decode Application Is Realized on Open Virtual Platform
Written By Duncan Graham and Dhaval Shah
With software development eating up more resources than hardware development, it’s time for a freer and more open approach. more...

Top 10 Tips for efficient Perl Scripting for Chip Designers
Written By Umang Mistry - Sibridge Technologies
Bringing automation to ASIC design typically includes the use of “Scripts”. In the new competitive generation of chip designing where Time-to-Market is so critical, you need a way to finish your automation tasks in smarter ways. more...

Verification Management: The Path of Evolution (Portable design magazine)
Written By Rahul V. Shah and Darron May, ASIC Engg. - Sibridge Technologies and Mentor Graphics
You have gigabytes of verification data - what does it all mean? Verification management is both the next hurdle and the next path in verification evolution. more...

Migrating Ethernet VIP to OVM Is a Cinch (Verification Horizons of Mantor Graphics)
Our Partners’ Corner article from our friends at Sibridge Technologies, one of our Questa Vanguard Partners more...

Gigabit Ethernet VIP in SystemVerilog
The Sibridge Gigabit Ethernet (GBE) Verification IP is a reusable, configurable, pre-verified, plug-and-play verification component developed in System Verilog. more...

Getting the most out of your Bug tracking system
Bug tracking systems play a key role in the verification stage of a chips development cycle. Freely available Bug Tracking Systems (BTS) like Bugzilla and Mantis facilitate the process of tracking and reporting bugs. more...

Welcome to a Brave New World of HVLs
A few years ago, the ASIC industry used two HDLs for ASIC development, Verilog and VHDL. Soon C and C++ were viewed as a means to reduce the complexity of verification more...