Migrating From Verilog To System Verilog: Brave New World Of Soc Verification

Rahul V Shah
Sibridge Technologies
rahulv.shah@sibridgetech.com

Abstract: A few years ago, the ASIC industry used two HDLs for ASIC development, Verilog and VHDL. Soon C and C++ were viewed as a means to reduce the complexity of verification. But as the complexity of the chips grew, more languages came to the rescue: HVLs (High-Level Verification Languages) in different flavors emerged with “e”, “Vera” and ‘System Verilog” among the top three contenders as far as verification is concerned. This paper chronicles a Verilog verification engineer’s experience of migrating from the world of older HDL languages into the brave new world of HVLs like” System Verilog”.

There were great old days when people use to talk about Verilog and VHDL in terms of “Hardware Design Language (HDL)” and I would also say “Hardware Verification Languages (HVL)” since those were the only two which were also used for verification of the design. As the industry grew rapidly, the term “Time To Market (TTM)” came into picture. The trend of “C” Level modeling for verification came into existence to help out with more complex functions for which these designs were built,.

But as Moore’s law held true, the complexity kept on increasing, starting a race between the gate-counts of chips and what the current EDA tools could support. Soon it gave birth to many different approaches to handle the new complex chips and still meet TTM requirements. Many tools and languages came into existence including various new verification languages, emulations boards; hardware accelerators to speed up the process of verification. Like any other new language, engineers took time to validate and accept the new HVLs. System Verilog, Specman and Vera are the main members of the HVL family. These languages were designed just for “Verification”; they are promoted truly as verification languages and provide plenty of features to make verification easy.

But if you ask a verification engineer coming from a basic Verilog background, the first question will pop into his head is “What’s the big deal? Anything you can do in these languages I can still do the same using Verilog. So, why learn a new language and syntax and pay for it too?” To answer some of these questions let’s look at some of the key features of these HVL languages.

Powerful Randomization: Before I switched over to System Verilog based verification, if someone would have told me that “HVL has a very powerful randomization engine” my reaction would be:“I have the complete elaborated test plan in place. I have each and very possible condition well mapped out and I have taken care of everything.” But, normally we take care of all the conditions we can think about, but we cannot go beyond that. No matter even we use the fancy random functions in Verilog and PERL we are still not really randomizing when compared to the same in an HVL like System Verilog. It can be described quite simply as “Verification engineer can only write testcases or which you can think, hence limiting you with the verification engineer’s experience”.