SPI Slave Design IP

Sibridge Technologies’ SPI Slave IP is a Serial Peripheral Interconnect Slave. It performs full duplex synchronous 8 bit data transfers. User can able to specify SCLK phase, SCLK polarity, and LSB first to accommodate most SPI protocols.

  • Silicon proven IPs
  • High performance cores with low gate count
  • Modular architecture enabling easy integration
  • IP customization and integration
  • Comprehensive documentation for ease of use
  • Dedicated support team of domain experts

  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation